Phase-locked loops (PLLs) are often used as clock regenerators or frequency synthesizers in digital systems. For example, PLLs are used in a wide variety of applications in areas such as communication devices and other types of digital electronics. PLLs can be designed to operate in either a single-ended or differential fashion. As compared to a single-ended phase-locked loop (PLL), a differential PLL provides greater immunity to substrate noise, power supply or ground voltage fluctuations, and other undesirable effects. Despite the advantages provided by a differential PLL, problems arise in their design for low-power-supply-voltages such as a sub one-volt (1 V) power supply.
These problems may be further explained with respect to a conventional differential PLL 100 as illustrated in FIG. 1. Differential PLL 100 adjusts the output frequency and/or phase of a clock signal 110 synthesized by a voltage-controlled oscillator (VCO) 120 so as to match a reference clock signal (Refclk) 130. The VCO-produced clock signal 110 loops back as a feedback signal through a loop divider 140 that translates the frequency of the clock signal 110 to become a VCO-divided signal 105. A phase detector 150 then compares the phases of VCO divided signal 105 and the reference clock signal. Based upon this comparison, the phase detector adjusts the pulse widths for differential up and down voltages. The differential up voltage is comprised of an up positive voltage (upp) and an up negative voltage (upn). Similarly, the differential down voltage is comprised of a down positive voltage (dnp) and a down negative voltage (dnn). A conventional charge pump 160 adjusts a differential control voltage (formed from VCTP and VCTN) according to the relative pulse widths for the differential up and down voltages. A loop filter 170 then filters the differential control voltage using capacitive loads before the differential control voltage is received by the VCO, which then adjusts the clock signal accordingly.
As known in the art, the VCTP and VCTN voltages (which together form the differential control voltage) produced by the charge pump will vary with respect to a common mode voltage. Depending upon the necessary control of the clock signal, VCTP will vary from the common mode voltage whereas VCTN will vary in a complementary fashion from the common mode voltage. In other words, if VCTP increases from the common-mode voltage in response to the differential up voltage having a greater pulse width than the differential down voltage, VCTN will decrease the same amount from the common-mode voltage. Alternatively, if VCTN increases from the common-mode voltage in response to the differential down voltage having a greater pulse width than the differential up voltage, VCTP will decrease the same amount from the common-mode voltage. To maintain the common mode voltage for both signals, the charge pump will typically possess a common-mode feedback loop comprised of differential transistor pairs (not illustrated). But as a supply voltage (not illustrated) for differential PLL 100 is decreased, the available dynamic range for VCTP and VCTN will decrease accordingly. For example, suppose the supply voltage is 1 V. Such a value for the supply voltage leaves a maximum of 1 V of dynamic range for both VCTP and VCTN. However, this dynamic range cannot be fully exploited because the differential transistor pairs used in the feedback loop to maintain the common mode voltage cannot be driven “rail-to-rail,” i.e., between ground and the supply voltage. In such a case, neither VCTP nor VCTN could be varied through the full 1 V available dynamic range. Instead, a more limited dynamic range would have to be used to keep the differential transistor pairs in the common-mode feedback loop operating correctly. This limited dynamic range may not be enough to keep differential PLL 100 within the proper operating range.
Thus, there is a need in the art for improved differential PLL designs for use with low power supply voltages.